Implementation of reversible vedic multiplier for low latency and reduced resources utilization applications
نویسندگان
چکیده
منابع مشابه
Design and Implementation of an Efficient Vedic Multiplier for High Performance and Low Power Applications
This paper describes the work done towards design and implementation of multiplier modules using high speed architectures based on the concept of Vedic Mathematics. Unlike other Vedic multipliers where entire architecture is based on generating partial products in parallel and adding them, here the partial products for top level entity are adjusted using concatenation operation and are added us...
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ژورنال
عنوان ژورنال: IJARCCE
سال: 2014
ISSN: 2278-1021
DOI: 10.17148/ijarcce.2014.31238